failing like never before

Seven-Segment Display in VHDL

I wrote my first VHDL project last night during lab, andgot to see my design come to life when I programmed it into a Spartan3 FPGA. It was a pretty basic program, that changed a seven-segment display (like those old LED screens on old calculators) based on which switches were flipped. The four switches used were a BCD (Binary Encoded Decimal) value, so if the first and fourth switches were on and the second and third switches were off, then the BCD value would be 9 (1001). The seven-segment display would then display the value "9" if the switches were in position 1001. Fairly simple to design and program, but quite fun to play with. My VHDL code is below.


entity seven_segment is

port(
    x3,x2,x1,x0: in std_logic;
    a,b,c,d,e,i,g: out std_logic
);

end seven_segment;

architecture Behavioral of seven_segment is

begin
    a <= NOT( x1 OR x3 OR (x2 AND x0) OR (NOT(x2) AND NOT(x0)) );
    b <= NOT( NOT(x2) OR x3 OR (x1 AND x0) OR (NOT(x1) AND NOT(x0)) );
    c <= NOT( x3 OR x2 OR x0 OR (NOT(x0) AND NOT(x1)) );
    d <= NOT( x3 OR (NOT(x0) AND NOT(x2)) OR (x1 AND NOT(x0)) OR
        (x1 AND NOT(x2)) OR (x2 AND x0 AND NOT(x1)) );
    e <= NOT( (x1 AND NOT(x0)) OR (NOT(x2) AND NOT(x0)) );
    i <= NOT( x3 OR (NOT(X0) AND NOT(x1)) OR (x2 AND NOT(X0) AND x1) OR
        (x2 AND NOT(x1)) );
    g <= NOT( x3 OR (NOT(x1) AND x2) OR (x1 AND NOT(x0)) OR
        (x1 and NOT(x2)) );

end Behavioral;